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Text File  |  2000-02-28  |  8KB  |  190 lines
  1. #ifndef WARPUP_MACROS_H
  2. #define WARPUP_MACROS_H
  3.  
  4. #define PPCLIBCALLASM    "\n\
  5.     stwu    1,-32(1)\n\
  6.     mflr    12\n\
  7.     stw    12,28(1)\n\
  8.     mfcr    12\n\
  9.     stw    12,24(1)\n\
  10.     mtlr    0\n\
  11.     blrl\n\
  12.     lwz    12,24(1)\n\
  13.     mtcr    12\n\
  14.     lwz    12,28(1)\n\
  15.     mtlr    12\n\
  16.     la    1,32(1)\n\
  17.     "
  18.  
  19. #define PPCLP0(base,offs,rt)                    \
  20. ({                                \
  21.     register rt returnreg __asm("3");            \
  22.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  23.     __asm volatile(PPCLIBCALLASM                \
  24.     :"=r" (returnreg)                    \
  25.     :"r" (dummy)                        \
  26.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  27.     returnreg;\
  28. })
  29.  
  30. #define PPCLP0NR(base,offs)                    \
  31. ({                                \
  32.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  33.     __asm volatile(PPCLIBCALLASM                \
  34.     :                            \
  35.     :"r" (dummy)                        \
  36.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  37. })
  38.  
  39. #define PPCLP1(base,offs,rt,t1,r1,v1)                \
  40. ({                                \
  41.     register rt returnreg __asm("3");            \
  42.     register t1 param1 __asm(#r1)=(v1);            \
  43.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  44.     __asm volatile(PPCLIBCALLASM                \
  45.     :"=r" (returnreg)                    \
  46.     :"r" (dummy),"r" (param1)                \
  47.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  48.     returnreg;\
  49. })
  50.  
  51. #define PPCLP1NR(base,offs,t1,r1,v1)                \
  52. ({                                \
  53.     register t1 param1 __asm(#r1)=(v1);            \
  54.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  55.     __asm volatile(PPCLIBCALLASM                \
  56.     :                            \
  57.     :"r" (dummy),"r" (param1)                \
  58.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  59. })
  60.  
  61. #define PPCLP2(base,offs,rt,t1,r1,v1,t2,r2,v2)            \
  62. ({                                \
  63.     register rt returnreg __asm("3");            \
  64.     register t1 param1 __asm(#r1)=(v1);            \
  65.     register t2 param2 __asm(#r2)=(v2);            \
  66.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  67.     __asm volatile(PPCLIBCALLASM                \
  68.     :"=r" (returnreg)                    \
  69.     :"r" (dummy),"r" (param1),"r" (param2)            \
  70.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  71.     returnreg;\
  72. })
  73.  
  74. #define PPCLP2NR(base,offs,t1,r1,v1,t2,r2,v2)            \
  75. ({                                \
  76.     register t1 param1 __asm(#r1)=(v1);            \
  77.     register t2 param2 __asm(#r2)=(v2);            \
  78.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  79.     __asm volatile(PPCLIBCALLASM                \
  80.     :                            \
  81.     :"r" (dummy),"r" (param1),"r" (param2)            \
  82.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  83. })
  84.  
  85. #define PPCLP3(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3)        \
  86. ({                                \
  87.     register rt returnreg __asm("3");            \
  88.     register t1 param1 __asm(#r1)=(v1);            \
  89.     register t2 param2 __asm(#r2)=(v2);            \
  90.     register t3 param3 __asm(#r3)=(v3);            \
  91.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  92.     __asm volatile(PPCLIBCALLASM                \
  93.     :"=r" (returnreg)                    \
  94.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3)    \
  95.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  96.     returnreg;\
  97. })
  98.  
  99. #define PPCLP3NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3)        \
  100. ({                                \
  101.     register t1 param1 __asm(#r1)=(v1);            \
  102.     register t2 param2 __asm(#r2)=(v2);            \
  103.     register t3 param3 __asm(#r3)=(v3);            \
  104.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  105.     __asm volatile(PPCLIBCALLASM                \
  106.     :                            \
  107.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3)    \
  108.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  109. })
  110.  
  111. #define PPCLP4(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4)\
  112. ({                                \
  113.     register rt returnreg __asm("3");            \
  114.     register t1 param1 __asm(#r1)=(v1);            \
  115.     register t2 param2 __asm(#r2)=(v2);            \
  116.     register t3 param3 __asm(#r3)=(v3);            \
  117.     register t4 param4 __asm(#r4)=(v4);            \
  118.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  119.     __asm volatile(PPCLIBCALLASM                \
  120.     :"=r" (returnreg)                    \
  121.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4)    \
  122.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  123.     returnreg;\
  124. })
  125.  
  126. #define PPCLP4NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4)        \
  127. ({                                \
  128.     register t1 param1 __asm(#r1)=(v1);            \
  129.     register t2 param2 __asm(#r2)=(v2);            \
  130.     register t3 param3 __asm(#r3)=(v3);            \
  131.     register t4 param4 __asm(#r4)=(v4);            \
  132.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  133.     __asm volatile(PPCLIBCALLASM                \
  134.     :                            \
  135.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4)    \
  136.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  137. })
  138.  
  139. #define PPCLP5(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5)\
  140. ({                                \
  141.     register rt returnreg __asm("3");            \
  142.     register t1 param1 __asm(#r1)=(v1);            \
  143.     register t2 param2 __asm(#r2)=(v2);            \
  144.     register t3 param3 __asm(#r3)=(v3);            \
  145.     register t4 param4 __asm(#r4)=(v4);            \
  146.     register t5 param5 __asm(#r5)=(v5);            \
  147.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  148.     __asm volatile(PPCLIBCALLASM                \
  149.     :"=r" (returnreg)                    \
  150.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5)    \
  151.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  152.     returnreg;\
  153. })
  154.  
  155. #define PPCLP6(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6)\
  156. ({                                \
  157.     register rt returnreg __asm("3");            \
  158.     register t1 param1 __asm(#r1)=(v1);            \
  159.     register t2 param2 __asm(#r2)=(v2);            \
  160.     register t3 param3 __asm(#r3)=(v3);            \
  161.     register t4 param4 __asm(#r4)=(v4);            \
  162.     register t5 param5 __asm(#r5)=(v5);            \
  163.     register t6 param6 __asm(#r6)=(v6);            \
  164.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  165.     __asm volatile(PPCLIBCALLASM                \
  166.     :"=r" (returnreg)                    \
  167.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6)    \
  168.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  169.     returnreg;\
  170. })
  171.  
  172. #define PPCLP7(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6,t7,r7,v7)\
  173. ({                                \
  174.     register rt returnreg __asm("3");            \
  175.     register t1 param1 __asm(#r1)=(v1);            \
  176.     register t2 param2 __asm(#r2)=(v2);            \
  177.     register t3 param3 __asm(#r3)=(v3);            \
  178.     register t4 param4 __asm(#r4)=(v4);            \
  179.     register t5 param5 __asm(#r5)=(v5);            \
  180.     register t6 param6 __asm(#r6)=(v6);            \
  181.     register t7 param7 __asm(#r7)=(v7);            \
  182.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  183.     __asm volatile(PPCLIBCALLASM                \
  184.     :"=r" (returnreg)                    \
  185.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6),"r" (param7)    \
  186.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","memory");\
  187.     returnreg;\
  188. })
  189. #endif
  190.